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Cypress CY7C1019D User Manual

Mbit (128k x 8) static ram, Features, Functional description

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CY7C1019D

1-Mbit (128K x 8) Static RAM

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-05464 Rev. *E

Revised February 22, 2007

Features

• Pin- and function-compatible with CY7C1019B

• High speed

— t

AA

= 10 ns

• Low active power

— I

CC

= 80 mA @ 10 ns

• Low CMOS standby power

— I

SB2

= 3 mA

• 2.0V Data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Center power/ground pinout

• Easy memory expansion with CE

and OE options

• Functionally equivalent to CY7C1019B

• Available in Pb-free 32-pin 400-Mil wide Molded SOJ and

32-pin TSOP II packages

Functional Description

[1]

The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected. The eight input
and output pins (IO

0

through IO

7

) are placed in a

high-impedance state when:

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

• When the write operation is active (CE LOW, and WE LOW).

Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight IO pins (IO

0

through IO

7

) is then written into the location specified on the

address pins (A

0

through A

16

).

Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the IO pins.

Logic Block Diagram

A0

IO0

IO7

IO1
IO2
IO3
IO4
IO5
IO6

A1

A2

A3

A4

A5

A6

A7

A8

A

9

SENSE AMPS

POWER

DOWN

CE

WE

OE

A

10

A

11

A

12

A

13

A

14

ROW DECODER

COLUMN DECODER

128K x 8

ARRAY

INPUT BUFFER

A

15

A

16

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at

www.cypress.com

.

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