Cypress CY7C1241V18 - Manual (Page 3)

CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 3 of 28
Logic Block Diagram (CY7C1243V18)
Logic Block Diagram (CY7C1245V18)
51
2K x 18 Arra
y
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Re
ad Add. Decode
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
18
72
18
BWS
[1:0]
V
REF
W
rite Add. Decode
Write
Reg
36
A
(18:0)
19
51
2K x 18 Arra
y
51
2K x 18 Arra
y
51
2K x 18 Arra
y
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
2
56K x 36
A
rray
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add.
Deco
de
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
18
36
144
36
BWS
[3:0]
V
REF
W
rite Add.
Decode
Write
Reg
72
A
(17:0)
18
2
56K x 36
A
rray
2
56K x 36
A
rray
2
56K x 36
A
rray
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
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