Cypress CY14B104L - Manual (Page 10)

CY14B104L, CY14B104N
Document #: 001-07102 Rev. *L Page 10 of 25
Figure 7. SRAM Read Cycle #2: CE and OE Controlled
[3, 14, 18]
Figure 8. SRAM Write Cycle #1: WE Controlled
[3, 17, 18, 19]
$GGUHVV9DOLG $GGUHVV
'DWD2XWSXW 2XWSXW'DWD9DOLG
6WDQGE\
$FWLYH
+LJK,PSHGDQFH
&(
2(
%+(%/(
,
&&
W
+=&(
W
5&
W
$&(
W
$$
W
/=&(
W
'2(
W
/=2(
W
'%(
W
/=%(
W
38 W
3'
W
+=%(
W
+=2(
'DWD2XWSXW
'DWD,QSXW ,QSXW'DWD9DOLG
+LJK,PSHGDQFH
$GGUHVV9DOLG $GGUHVV
3UHYLRXV'DWD
W
:&
W
6&(
W
+$
W
%:
W
$:
W
3:(
W
6$
W
6'
W
+'
W
+=:(
W
/=:(
:(
%+(%/(
&(
Notes
19. CE or WE must be >V
IH
during address transitions.
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