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Ddr3 timing items, 1t/2t command timing, Cas# latency – chiliGREEN GA-A75M-UD2H User Manual

Page 40: Ras to cas r/w delay, Row precharge time, Minimum ras active time, Twtr command delay, Trfc0 for dimm2, dimm4, Trfc1 for dimm1, dimm3, Write recovery time

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BIOS Setup

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DDR3 Timing Items

Manual allows all DDR3 Timing items below to be configurable.

Options are: Auto (default), Manual.

1T/2T Command Timing

Options are: Auto (default), 1T, 2T.

CAS# latency

Options are: Auto (default), 5T~14T.

RAS to CAS R/W Delay

Options are: Auto (default), 5T~14T.

Row Precharge Time

Options are: Auto (default), 5T~14T.

Minimum RAS Active Time

Options are: Auto (default), 15T~36T.

TwTr Command Delay

Options are: Auto (default), 4T~8T.

Trfc0 for DIMM2, DIMM4

Options are: Auto (default), 90ns, 110ns, 160ns, 300ns, 350ns.

Trfc1 for DIMM1, DIMM3

Options are: Auto (default), 90ns, 110ns, 160ns, 300ns, 350ns.

Write Recovery Time

Options are: Auto (default), 5T~8T, 10T, 12T, 14T, 16T.

Precharge Time

Options are: Auto (default), 4T~8T.

Row Cycle Time

Options are: Auto (default), 20T~54T.

RAS to RAS Delay

Options are: Auto (default), 4T~8T.

Four Bank Activate Window

Options are: Auto (default), 16T~40T.

DRAM Configuration

CMOS Setup Utility-Copyright (C) 1984-2011 Award Software

DRAM Configuration

DDR3 Timing Items

[Auto]

SPD

Auto

x 1T/2T Command Timing

Auto

--

--

x CAS# latency

Auto

9T

9T

x RAS to CAS R/W Delay

Auto

9T

9T

x Row Precharge Time

Auto

9T

9T

x Minimum RAS Active Time

Auto

24T

24T

x TwTr Command Delay

Auto

5T

5T

x Trfc0 for DIMM2, DIMM4

Auto

110ns

110ns

x Trfc1 for DIMM1, DIMM3

Auto

--

--

x Write Recovery Time

Auto

10T

6T

x Precharge Time

Auto

5T

4T

x Row Cycle Time

Auto

33T

20T

x RAS to RAS Delay

Auto

4T

4T

x Four Bank Activate Windows

Auto

--

--

Bank Interleaving

[Enabled]

higf

: Move

Enter: Select

+/-/PU/PD: Value

F10: Save

ESC: Exit

F1: General Help

F5: Previous Values

F6: Fail-Safe Defaults

F7: Optimized Defaults

Item Help

Menu Level 