Cirrus Logic AN186 - Manual (Page 4)

AN186
4 AN186REV1
4.1 Power-up Delay - 100us
Upon power-up, the EP72/73XX is in an unknown state. It must first be reset by the power-on reset signal (nPOR). nPOR (active
low) should be held low until the power supply reaches its operational voltage to initialize the EP72/73XX properly, and to allow
the RTC to stabilize. Since the power-on reset operates asynchronously to the system clock, it is not required to wait until the
system clock is stabilized. Therefore, the signal nPOR must be held low at 100us after the power supply has stabilized.
Afterwards, nPOR should be held high.
During normal operation (i.e., after the initial power-up) if nPOR is used to reset the EP72/73XX, it needs to be held low for at
least one clock cycle of the selected clock speed (e.g., when running at 13 MHz, the low pulse width needs to be > 1/13 MHz
= 77 ns). This is done to guarantee that it will be detected low.
If the EP72/73XX V
dd
core supply ever drops below the DC recommended operating range, the device must be fully reset to
guarantee that all internal logic is in a known state. This especially applies to the internal State Control logic block. This logic
block must be reset to guarantee proper operation of the device. To fully reset the device, nPOR must be used. The signals
nPWRFL and nURESET do not reset the State Control block.
When nPOR transitions from a low to high state, it latches several signals into the EP72/73XX. These signals are the following:
l Test[0:1]
l Port E[0:2]
l nURESET
l DRIVE[0:1]
l nMEDCHG
Since the levels of each of the above signals are latched upon nPOR rising, they need to have settled to their desired level. The
recommended method of accomplishing this is by tying each of the signals directly to V
dd
or gnd, or by pulling them either high
or low. Test[0:1] and nURESET are latched upon reset to determine if the EP72/73XX should enter a Test mode upon power-
up. For normal operation, all three signals should be either tied or pulled high. See the product data sheet for a description of
each of the other signals.
4.2 1 to 2 Second Delay
A power-up or cold boot delay occurs when power is first applied to the EP72/73XX. However, it can also occur after a battery
change or power failure. A power failure could occur due to the battery or wall powered supply voltage dropping below a
predefined level.
Built into the EP72/73XX is a circuit that has been created to prevent the EP72/73XX from exiting the Standby State due to a
false battery GOOD indication caused by alkaline battery recovery. The circuit requires that the power supply voltage be at the
acceptable level for at least one second. The EP72/73XX implements this by conditioning several signals into another
deglitcher. This deglitcher is clocked by a 1 Hz clock source, derived from the RTC. Therefore, the power to the EP72/73XX
must be stable for at least 2 seconds (i.e., a minimum of two 1 Hz clock edges). The signals supplied to this deglitcher are the
following:
l nPOR
l nPWRFL
l BATOK
l nEXTPWR
In order for the output of this deglitcher to become active, it must have the signals nPOR and nPWRFL = 1, and either BATOK
= 1 or nEXTPWR = 0.
After the above criteria is met, there are two methods that can be used to exit the Standby State:
1) By using the WAKEUP signal, or
2) By receiving a keypress, RTC, external, or media change interrupt. In order for this to work, the KBWEN bit must be
set in the SYSCON2 register.