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Figure 5. conversion/acquisition cycle timing, Figure 6. bit representation/storage in 68hc05, Conclusion – Cirrus Logic AN131 User Manual

Page 5: An131

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AN131

AN131REV2

5

5. CONCLUSION

This application note presents an example of how
to interface the CS5521/22/23/24/28 to the
68HC05. It is divided into two main sections: hard-
ware and software. The hardware interface illus-
trates both three-wire and a four-wire interface.
The three-wire interface is SPI and Microwire™
compatible. The software section illustrates how to
initialize the converter and microcontroller, write
to the CSRs, write and read the ADC’s internal reg-
isters, perform calibrations, and acquire conver-
sions. The software is modularized and provides
important subroutines such as write_register,
read_register
,

write_csrs and convert, which were

all written in 68HC05 assembly language.

The software described in the note is included in
Section 6. “APPENDIX: 68HC05 Microcode to In-
terface to the CS5521/22/23/24/28” on page 6.

Command Time

8 SCLKs

8 SCLKs Clear SDO Flag

Data SDO Continuous Conversion Read

SDO

SCLK

SDI

t *

d

Data Time

24 SCLKs

MSB

LSB

* td = XIN/OWR clock cycles for each conversion except the

first conversion which will take XIN/OWR + 7 clock cycles

XIN/OWR

Clock Cycles

Figure 5. Conversion/Acquisition Cycle Timing

MSB

High-Byte

Mid-Byte

Low-Byte

A) 24-Bit Conversion Data Word (CS5522/24/28)

MSB

High-Byte

Mid-Byte

Low-Byte

B) 16-Bit Conversion Data Word (CS5521/23)

0- always zero, 1- always one,

CI1, CI0 - Channel Indicator Bits

OD - Oscillation Detect, OF - Overflow

Figure 6. Bit Representation/Storage in 68HC05

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1

1

1

0

CI1

CI0

OD

OF