Cirrus Logic AN131 - Manual (Page 12)

AN131
12 AN131REV2
;* Routine - delay
;* Input - count in ACCA
;* Output - none
;* This routine delays by using the count specified in ACCA. The 68HC05
;* Development Board uses a 4.0MHz clock (E = 2.0MHz), thus each cycle is
;* 500ns. This delay is equivalent to (500ns)*(1545)(count value)
;* A count of 720 provides a 556ms delay.
;*****************************************************************************
delay NOP
outlp: CLRX ;X used as inner loop count
innlp: DECX ;256 loops on inner
NOP ;2 cycles
NOP ;2 cycles
BNE innlp ;10 cycles*256*500ns=1.28ms
DECA ;countdown accumulator
BNE outlp ;2569 cycles*500ns*ACCA
RTS ;Return
;*****************************************************************************
;* Interrupt Vectors
;*****************************************************************************
NOT_USEDRTI ;Return from interrupt
ORG $1FF4 ;Int Vector location
FDB NOT_USED ;SPI interrupt
FDB NOT_USED ;SPI interrupt
FDB NOT_USED ;SPI interrupt
FDB NOT_USED ;SPI interrupt
FDB NOT_USED ;SPI interrupt
FDB MAIN ;Reset interrupt - power on reset