Cirrus Logic AN131 - Manual (Page 3)

AN131
AN131REV2 3
ing the number of Setups to be accessed and sub-
tracting 1. Because each CSR holds two Setups,
this number must always be an odd value, that is,
DP0 must always be logic 1 when reading and writ-
ing the CSRs. To modify the Depth Pointer bits, the
configuration register is read to prevent corruption
of other bits. After the read_register routine is run
with the command 0x0B (HEX), the DP3-DP0 bits
are masked to “0011”. Then, the updated informa-
tion is written back into the ADC with the com-
mand 0x03 (HEX) using the write_register routine.
After the depth pointer bits are set correctly, the
CSR information is written to the ADC. The com-
mand 0x05 (HEX) is sent to the ADC to begin the
write sequence (to read the CSRs, the command
would be 0x0D). At this point, the ADC is expect-
ing to receive information for two 24-bit CSRs, or
48 bits, based on the Depth Pointer bits. The first
CSR is written with a value of 0x000000 (HEX).
This sets Setup 1 and Setup 2 both to convert bipo-
lar, 100mV signals on physical channel 1 (PC1) at
an output word rate (OWR) of 15 Hz, and latch pins
A1-A0 equal to “00”. The second CSR is written
with the value 0x4C0105 (HEX). This sets Setup 3
to convert a bipolar, 100mV signal on PC2 at a
101.1 Hz OWR, with latch pins A1-A0 at “01”.
This also sets Setup 4 to convert a unipolar, 25mV
input signal at 15 Hz on PC3, with output latch pins
A1-A0 set to “00”.
3.3 Self-Offset Calibration
Calibrate is a subroutine that performs a self-offset
calibration using Setup 1. Calibrate does this by
sending the command 0x81 (HEX) to the ADC
through the SPI. This tells the ADC to perform a
self-offset calibration using Setup 1 (see the
CS5522/24/28 and CS5521/23 Data Sheets for in-
formation on performing offset or gain calibrations
using other Setups). Once the command has been
sent, the controller polls MISO (SDO) until it falls,
indicating that the calibration is complete. Note
that although calibrations are done using a specific
Setup, the offset or gain register that is modified
belongs to the physical channel referenced by that
Setup.
3.4 Read/Write Gain Register
The routine rwgain provides an example of how to
modify the ADC’s internal gain registers. To mod-
ify the gain register the command byte and data
byte variables are written with the appropriate in-
formation. rwgain then calls the subroutine
write_register, which uses these variables to set the
contents of Physical Channel 1 (PC1)’s gain regis-
ter to 0x800000 (HEX). The write_register routine
calls the send_spi algorithm four times, once to
send the command byte, and three more times to
send the three data bytes. Send_spi is a subroutine
which transfers data to the CS5521/22/23/24/28
MSB-first through the SPI. Figure 3 depicts the
timing diagram for the write-cycle in the
CS5521/22/23/24/28’s serial port. It is important to
note here that this section of the code demonstrates
how to write to the gain register of PC1. It does not
perform a gain calibration. To write to the other in-
ternal registers of the ADC, follow the procedures
outlined in the CS5522/24/28 and CS5521/23 data
sheets.
To read the value in the gain register of PC1, the
command byte is loaded with the value 0x0A
(HEX), and the read_register routine is called. It
duplicates the read-cycle timing diagram depicted
in Figure 4. Read_register calls send_spi once to
transfer the command-byte to the
CS5521/22/23/24/28. This places the converter
into the data state where it waits until data is read
from its serial port. Read_register then calls
receive_spi three times and transfers three bytes of
information from the CS5521/22/23/24/28 to the
68HC05. Similar to send_spi, receive_spi acquires
a byte one bit at a time, MSB-first from the SPI.
When the transfer is complete, the variables
high_byte, mid_byte, and low_byte contain the val-
ue present in PC1’s 24-bit gain register.