Cirrus Logic AN130 - Manual (Page 9)

AN130
AN130REV2 9
;* Input - none
;* Output - none
;* This subroutine writes to and reads from the gain register on physical
;* channel 1.
;*****************************************************************************
modify_gain MOVLW 0x02 ; Command to write Gain register
MOVWF COMMAND ; Set command byte
MOVLW 0x80 ; High byte information
MOVWF HIGHBYTE ; Set high byte
CLRF MIDBYTE ; Set middle byte
CLRF LOWBYTE ; Set low byte
CALL write_register ; Write 0x800000 to Gain Register
MOVLW 0x0A ; Command to read Gain Register
MOVWF COMMAND ; Set Command byte
CALL read_register ; Read data from the Gain Register
RETURN ; Exit
;*****************************************************************************
;* Routine - write_csrs
;* Input - none
;* Output - none
;* This subroutine is used to modify the information in the Channel Setup
;* Registers. It first changes the depth pointer bits in the ADCs config.
;* register to reflect the number of CSRs to be written, and then writes to
;* the appropriate CSRs
;*****************************************************************************
write_csrs MOVLW 0x0B ; Command to read Config. Register
MOVWF COMMAND ; set command byte
CALL read_register ; read the config. register
;*** Mask DP3-DP0 to access two CSRs (four Setups) ***
MOVLW 0x3F ; mask DP3-DP2 low
ANDWF MIDBYTE, 1 ; change DP3 and DP2
MOVLW 0x30
; mask DP1-DP0 high
IORWF MIDBYTE, 1 ; change DP1 and DP0
MOVLW 0x03 ; Command to write config. register
MOVWF COMMAND ; set command byte
CALL write_register ; Change Depth Pointer Bits
;*** Write to CSRs - note, the ADC expects information for the
;
number CSRs indicated in the Depth Bits (DP3-0 in the
; configuration register) so all of the CSRs are
; written at this time ***