Cirrus Logic AN130 - Manual (Page 3)

AN130
AN130REV2 3
DP0 must always be logic 1 when reading and writ-
ing the CSRs. To modify the Depth Pointer bits, the
configuration register is read to prevent corruption
of other bits. After the read_register routine is run
with the command 0x0B (HEX), the DP3-DP0 bits
are masked to “0011”. Then, the updated informa-
tion is written back into the ADC with the com-
mand 0x03 (HEX) using the write_register routine.
After the depth pointer bits are set correctly, the
CSR information is written to the ADC. The com-
mand 0x05 (HEX) is sent to the ADC to begin the
write sequence (to read the CSRs, the command
would be 0x0D). At this point, the ADC is expect-
ing to receive information for two 24-bit CSRs, or
48 bits, based on the Depth Pointer bits. The first
CSR is written with a value of 0x000000 (HEX).
This sets Setup 1 and Setup 2 both to convert bipo-
lar, 100mV signals on physical channel 1 (PC1) at
an output word rate (OWR) of 15 Hz, and latch pins
A1-A0 equal to “00”. The second CSR is written
with the value 0x4C0105 (HEX). This sets Setup 3
to convert a bipolar, 100mV signal on PC2 at a
101.1 Hz OWR, with latch pins A1-A0 at “01”.
This also sets Setup 4 to convert a unipolar, 25mV
input signal at 15 Hz on PC3, with output latch pins
A1-A0 set to “00”.
3.3 Self-Offset Calibration
Calibrate is a subroutine that performs a self-offset
calibration using Setup 1. Calibrate does this by
sending the command 0x81 (HEX) to the ADC.
This tells the ADC to perform a self-offset calibra-
tion using Setup 1 (see the CS5521/22/23/24/28
Data Sheet for information on performing offset or
gain calibrations using other Setups). Once the
command has been sent, the controller polls RA2
(SDO) until it falls, indicating that the calibration is
complete. Note that although calibrations are done
on a specific Setup, the offset or gain register that
is modified belongs to the physical channel refer-
enced by that Setup.
3.4 Read/Write Gain Register
The routine modify_gain provides an example of
how to modify the ADC’s internal gain registers.
To modify the gain register the command byte and
data byte variables are written with the appropriate
information. Modify_gain then calls the subroutine
write_register, which uses these variables to set the
contents of Physical Channel 1 (PC1)’s gain regis-
ter to 0x800000 (HEX). The write_register routine
calls the send_byte algorithm four times, once to
send the command byte, and three more times to
send the three data bytes. Send_byte is a subroutine
used to ‘bit-bang’ a byte of information from the
PIC16C84 to the CS5521/22/23/24/28. A byte is
transferred one bit at a time, MSB (most significant
bit) first, by placing a bit of information on RA1
(SDI) and then pulsing RA3 (SCLK). The byte is
transferred by repeating this process eight times.
Figure 3 depicts the timing diagram for the write-
cycle in the CS5521/22/23/24/28’s serial port. It is
important to note here that this section of the code
demonstrates how to write to the gain register of
PC1. It does not perform a gain calibration. To
write to the other internal registers of the ADC, fol-
low the procedures outlined in the
CS5521/22/23/24/28 data sheet.
To read the value in the gain register of PC1, the
command byte is loaded with the value 0x0A
(HEX), and the read_register routine is called. It
duplicates the read-cycle timing diagram depicted
in Figure 4. Read_register asserts CS (RA0). Then
it calls send_byte once to transfer the command-
byte to the CS5521/22/23/24/28. This places the
converter into the data state where it waits until
data is read from its serial port. Read_register then
calls receive_byte three times and transfers three
bytes of information from the CS5521/22/23/24/28
to the PIC16C84. Similar to send_byte,
receive_byte acquires a byte one bit at a time, MSB
first. When the transfer is complete, the variables
high_byte, mid_byte, and low_byte contain the val-
ue present in PC1’s 24-bit gain register.