Cirrus Logic CS5361 - Manual (Page 12)

CS5361
12 DS467F2
Figure 13. Master Mode, Left Justified SAI Figure 14. Slave Mode, Left Justified SAI
SCLK output
tmslr
SDOUT
tsdo
LRCK
output
MSB MSB-1
CLK input
LRCK input
dss
t
MSB MSB-1 MSB-2
tsclkw
SDOUT
s rd l
t
Figure 15. Master Mode, I
2
S SAI Figure 16. Slave Mode, I
2
S SAI
SCLK input
LRCK input
MSB MSB-1
tsclkw
SDOUT
s rd l
t
dss
t
SCLK input
LRCK input
MSB MSB-1
tsclkw
SDOUT
s rd l
t
dss
t
OVFL
t setup
LRCK
t hold
Figure 17. OVFL Output Timing