4 mclk frequency - address 05h, 1 master clock dividers (bits 6:4), Table 9. mclk frequency – Cirrus Logic CS5345 User Manual
Page 34: 5 pgaout control - address 06h, 1 pgaout source select (bit 6), Table 10. pgaout source selection, 6 channel b pga control - address 07h, 1 channel b pga gain (bits 5:0), Mclk frequency - address 05h” on, Gain
34
DS658F4
CS5345
6.4
MCLK Frequency - Address 05h
6.4.1
Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See
6.5
PGAOut Control - Address 06h
6.5.1
PGAOut Source Select (Bit 6)
Function:
This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to
6.6
Channel B PGA Control - Address 07h
6.6.1
Channel B PGA Gain (Bits 5:0)
Function:
“Channel A PGA Gain (Bits 5:0)” on page 35.
7
6
5
4
3
2
1
0
Reserved
MCLK
Freq2
MCLK
Freq1
MCLK
Freq0
Reserved
Reserved
Reserved
Reserved
MCLK Divider
MCLK Freq2
MCLK Freq1
MCLK Freq0
ч 1
0
0
0
ч 1.5
0
0
1
ч 2
0
1
0
ч 3
0
1
1
ч 4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 9. MCLK Frequency
7
6
5
4
3
2
1
0
Reserved
PGAOut
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PGAOut
PGAOutA & PGAOutB
0
High Impedance
1
PGA Output
Table 10. PGAOut Source Selection
7
6
5
4
3
2
1
0
Reserved
Reserved
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0