Cirrus Logic CS5345 User Manual
Cs5345, A/d features, System features
Copyright
Cirrus Logic, Inc. 2012
(All Rights Reserved)
104 dB, 24-Bit, 192 kHz Stereo Audio ADC
A/D Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
–
± 12 dB Gain, 0.5 dB Step Size
–
Zero Crossing, Click-Free Transitions
Stereo Microphone Inputs
–
+32 dB Gain Stage
–
Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
–
Left-Justified up to 24-bit
–
I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
System Features
Power-Down Mode
+3.3 V to +5 V Analog Power Supply, Nominal
+3.3 V to +5 V Digital Power Supply, Nominal
Direct Interface with 1.8 V to 5 V Logic Levels
Pin-Compatible with CS4245
General Description
The CS5345 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5345 performs stereo analog-to-digi-
tal (A/D) conversion of up to 24-bit serial values at
sample rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of ± 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5345 and other devices operating over a
wide range of logic levels.
The CS5345 is available in a 48-pin LQFP package in
Commercial (-10° to +70° C) grade. The CDB5345 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to
“Ordering Information” on page 42
for complete
details.
1.8 V to 5 V
Low-Latency
Anti-Alias Filter
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo Input 1
Serial
Audio
Output
3.3 V to 5 V
3.3 V to 5 V
MUX
PGA
PCM S
e
ri
al
In
te
rfa
c
e
Register Configuration
Le
v
e
l
Tra
n
s
lat
or
Left PGA Output
Right PGA Output
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
PGA
+32 dB
+32 dB
Le
v
e
l Tr
an
s
la
to
r
Reset
I²C/SPI
Control Data
Interrupt
Overflow
AUG '12
DS658F4
CS5345
Document Outline
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- Specified Operating Conditions
- Absolute Maximum Ratings
- ADC Analog Characteristics
- ADC Analog Characteristics
- ADC Digital Filter Characteristics
- PGAOUT Analog Characteristics
- PGAOUT Analog Characteristics
- PGAOUT Analog Characteristics
- DC Electrical Characteristics
- Digital Interface Characteristics
- Switching Characteristics - Serial Audio Port
- Switching Characteristics - Control Port - I·C Format
- Switching Characteristics - Control Port - SPI Format
- 3. Typical Connection Diagram
- 4. Applications
- 4.1 Recommended Power-Up Sequence
- 4.2 System Clocking
- 4.3 High-Pass Filter and DC Offset Calibration
- 4.4 Analog Input Multiplexer, PGA, and Mic Gain
- 4.5 Input Connections
- 4.6 PGA Auxiliary Analog Output
- 4.7 Control Port Description and Timing
- 4.8 Interrupts and Overflow
- 4.9 Reset
- 4.10 Synchronization of Multiple Devices
- 4.11 Grounding and Power Supply Decoupling
- 5. Register Quick Reference
- 6. Register Description
- 6.1 Chip ID - Register 01h
- 6.2 Power Control - Address 02h
- 6.3 ADC Control - Address 04h
- 6.4 MCLK Frequency - Address 05h
- 6.5 PGAOut Control - Address 06h
- 6.6 Channel B PGA Control - Address 07h
- 6.7 Channel A PGA Control - Address 08h
- 6.8 ADC Input Control - Address 09h
- 6.9 Active Level Control - Address 0Ch
- 6.10 Interrupt Status - Address 0Dh
- 6.11 Interrupt Mask - Address 0Eh
- 6.12 Interrupt Mode MSB - Address 0Fh
- 6.13 Interrupt Mode LSB - Address 10h
- 7. Parameter Definitions
- 8. Filter Plots
- Figure 13. Single-Speed Stopband Rejection
- Figure 14. Single-Speed Stopband Rejection
- Figure 15. Single-Speed Transition Band (Detail)
- Figure 16. Single-Speed Passband Ripple
- Figure 17. Double-Speed Stopband Rejection
- Figure 18. Double-Speed Stopband Rejection
- Figure 19. Double-Speed Transition Band (Detail)
- Figure 20. Double-Speed Passband Ripple
- Figure 21. Quad-Speed Stopband Rejection
- Figure 22. Quad-Speed Stopband Rejection
- Figure 23. Quad-Speed Transition Band (Detail)
- Figure 24. Quad-Speed Passband Ripple
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History