Cirrus Logic CS5345 - Manual (Page 3)

DS658F4 3
CS5345
6.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 34
6.7 Channel A PGA Control - Address 08h .......................................................................................... 35
6.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 35
6.8 ADC Input Control - Address 09h ................................................................................................... 35
6.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 35
6.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 36
6.9 Active Level Control - Address 0Ch ................................................................................................ 36
6.9.1 Active High/Low (Bit 0) .......................................................................................................... 36
6.10 Interrupt Status - Address 0Dh ..................................................................................................... 36
6.10.1 Clock Error (Bit 3) ................................................................................................................ 37
6.10.2 Overflow (Bit 1) .................................................................................................................... 37
6.10.3 Underflow (Bit 0) .................................................................................................................. 37
6.11 Interrupt Mask - Address 0Eh ....................................................................................................... 37
6.12 Interrupt Mode MSB - Address 0Fh .............................................................................................. 37
6.13 Interrupt Mode LSB - Address 10h ............................................................................................... 37
7. PARAMETER DEFINITIONS ................................................................................................................ 38
8. FILTER PLOTS .................................................................................................................................. 39
9. PACKAGE DIMENSIONS .................................................................................................................... 41
10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 41
11. ORDERING INFORMATION ........................................................................................................ 42
12. REVISION HISTORY .......................................................................................................................... 42
LIST OF FIGURES
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 18
Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 18
Figure 3.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 19
Figure 4.Format 1, I²S up to 24-Bit Data ................................................................................................... 19
Figure 5.Control Port Timing - I²C Format ................................................................................................. 20
Figure 6.Control Port Timing - SPI Format ................................................................................................ 21
Figure 7.Typical Connection Diagram ....................................................................................................... 22
Figure 8.Master Mode Clocking ................................................................................................................ 24
Figure 9.Analog Input Architecture ............................................................................................................ 26
Figure 10.Control Port Timing in SPI Mode .............................................................................................. 27
Figure 11.Control Port Timing, I²C Write ................................................................................................... 28
Figure 12.Control Port Timing, I²C Read ................................................................................................... 28
Figure 13.Single-Speed Stopband Rejection ............................................................................................ 39
Figure 14.Single-Speed Stopband Rejection ............................................................................................ 39
Figure 15.Single-Speed Transition Band (Detail) ...................................................................................... 39
Figure 16.Single-Speed Passband Ripple ................................................................................................ 39
Figure 17.Double-Speed Stopband Rejection ........................................................................................... 39
Figure 18.Double-Speed Stopband Rejection ........................................................................................... 39
Figure 19.Double-Speed Transition Band (Detail) .................................................................................... 40
Figure 20.Double-Speed Passband Ripple ............................................................................................... 40
Figure 21.Quad-Speed Stopband Rejection ............................................................................................. 40
Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 40
Figure 23.Quad-Speed Transition Band (Detail) ....................................................................................... 40
Figure 24.Quad-Speed Passband Ripple ................................................................................................. 40
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 23
Table 2. Common Clock Frequencies ....................................................................................................... 23
Table 3. MCLK Dividers ............................................................................................................................ 24
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 24