Cirrus Logic CS5345 - Manual (Page 2)

2 DS658F4
CS5345
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ......................................................................................................................... 5
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
SPECIFIED OPERATING CONDITIONS ............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 7
ADC ANALOG CHARACTERISTICS ................................................................................................... 8
ADC ANALOG CHARACTERISTICS ................................................................................................. 10
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 11
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 12
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 13
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 14
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 15
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 16
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 17
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 20
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 21
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 22
4. APPLICATIONS ................................................................................................................................... 23
4.1 Recommended Power-Up Sequence ............................................................................................. 23
4.2 System Clocking ............................................................................................................................. 23
4.2.1 Master Clock ......................................................................................................................... 23
4.2.2 Master Mode ......................................................................................................................... 24
4.2.3 Slave Mode ........................................................................................................................... 24
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 24
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 26
4.5 Input Connections ........................................................................................................................... 26
4.6 PGA Auxiliary Analog Output ......................................................................................................... 26
4.7 Control Port Description and Timing ............................................................................................... 27
4.7.1 SPI Mode ............................................................................................................................... 27
4.7.2 I²C Mode ................................................................................................................................ 27
4.8 Interrupts and Overflow .................................................................................................................. 29
4.9 Reset .............................................................................................................................................. 29
4.10 Synchronization of Multiple Devices ............................................................................................. 29
4.11 Grounding and Power Supply Decoupling .................................................................................... 29
5. REGISTER QUICK REFERENCE ........................................................................................................ 31
6. REGISTER DESCRIPTION .................................................................................................................. 32
6.1 Chip ID - Register 01h .................................................................................................................... 32
6.2 Power Control - Address 02h ......................................................................................................... 32
6.2.1 Freeze (Bit 7) ......................................................................................................................... 32
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 32
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 32
6.2.4 Power-Down Device (Bit 0) ................................................................................................... 32
6.3 ADC Control - Address 04h ............................................................................................................ 33
6.3.1 Functional Mode (Bits 7:6) .................................................................................................... 33
6.3.2 Digital Interface Format (Bit 4) .............................................................................................. 33
6.3.3 Mute (Bit 2) ............................................................................................................................ 33
6.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 33
6.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 33
6.4 MCLK Frequency - Address 05h .................................................................................................... 34
6.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 34
6.5 PGAOut Control - Address 06h ...................................................................................................... 34
6.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 34
6.6 Channel B PGA Control - Address 07h .......................................................................................... 34