Cirrus Logic CRD48L10 - Manual (Page 25)

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3.2 MCU UI Controlled
Figure 3-24. Clocking for All S/PDIF Snapshots–DSP MCLK Slave
3.2.3 Snapshot Menu
A project defines the firmware modules downloaded to the DSP, and the data routing on the board. A snapshot is simply
a reconfiguration of the DSP using the same firmware and data routing. The default code released on the
CRD48L10-4in4out has snapshots for the S/PDIF project as described in
Section 3.2.2.4 . The snapshot menu selection
on the LCD appears as shown in Fig. 3-25 .
Figure 3-25. Snapshot Menu
3.2.4 AudioIn Source Menu
The CRD48L10-4in4out has an on-board codec for processing analog audio and an S/PDIF transceiver section which
allows digital audio in and out. Using the AudioIn Source selection on the LCD menu, the user can configure the
CRD48L10 to accept I
2 S data through the TP3 header. The AudioIn Source menu is shown in Fig. 3-26 .
Figure 3-26. AudioIn Source Menu
The following are menu choices under AudioIn Source:
• On–board
• External audio via TP3
3.2.5 Clock Source Menu
The CRD48L10-4in4out has a 12.288 MHz oscillator which is used to drive the REFCLK input of the CS48L10 and can be
used as accurate MCLK source. In some scenarios, it may be useful to use a different clock frequency on the CRD48L10
when attempting to emulate a particular system configuration. This can be accomplished using the “Clock Source” menu
of the MCU User Interface board. The snapshot menu selection on the LCD appears as shown in
Fig. 3-27 .
Figure 3-27. Clock Source Menu
Level
Translation
(CS48L10)
(CS42L73)
SPDIF RX
(CS8416 )
CLOCK MCLK1
MC
L
K
SCLK LRCLK
SCLK (ASP/XSP)
LRCLK (ASP/XSP)
SCLK
LRCLK
OSCILLATOR
12.288 MHz
Mini Optical RX
Or
1/8" Coax