3 speed control (address 03h), P 41, Cs43l21 – Cirrus Logic CS43L21 User Manual
Page 41
DS723F1
41
CS43L21
Function:
The entire D/A will enter a low-power state when this function is enabled. The contents of the control port
registers are retained in this mode.
6.3
Speed Control (Address 03h)
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the D/A when operating as a slave. When
AUTO is enabled, the MCLK/LRCK ratio must be implemented according to
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
Speed Mode (SPEED[1:0])
Default: 01
11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates
10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates
01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates
00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates
Function:
Sets the appropriate speed mode for the D/A in Master or Slave Mode. QSM is optimized for 8 kHz sample
rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled
(see
above).
Tri-State Serial Port Interface (3ST_SP)
Default: 0
0 - Disable
1 - Enable
Function:
When enabled and the device is configured as a master, the SCLK/LRCK signals are placed in a high-im-
pedance output state. If the serial port is configured as a slave, SCLK/LRCK are configured as inputs.
MCLK Divide By 2 (MCLKDIV2)
Default: 0
0 - Disabled
1 - Divide by 2
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
7
6
5
4
3
2
1
0
AUTO
SPEED1
SPEED0
3-ST_SP
Reserved
Reserved
Reserved
MCLKDIV2