Cirrus Logic CS4382A - Manual (Page 6)

6 DS618F2
CS4382A
1. PIN DESCRIPTION
Pin Name # Pin Description
VD 4 Digital Power (Input) - Positive power supply for the digital section.
GND
5
31
Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
LRCK 7
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
SDIN4 8
11
13
14
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK 9 Serial Clock (Input) - Serial clock for the serial audio interface.
VLC 18
Control Port Power (Input) - Determines the required signal level for the Control Port. Refer to the
Recommended Operating Conditions for appropriate voltages.
RST 19
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
FILT+ 20
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
VQ 21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be
used to bias the analog circuitry assuming there is no AC signal component and the DC current is less
than the maximum specified in the Analog Characteristics and Specifications section.
MUTEC1
MUTEC234 41
22
Mute Control (Output) - These pins are intended to be used as a control for external mute circuits to
prevent the clicks and pops that can occur in any single supply system. The use of external mute cir-
cuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous
clicks and pops.
SD
IN
3
GND
AOUTB2-
AOUTA3+
AOUTB3-
AOUTB2+
VA
AOUTA3-
AOUTB3+
AOUTA4-
AOUTA4+
6
2
4
8
10
1
3
5
7
9
11
12
13 14 15 16 17 18 19 20 21 22 23 24
31
35
33
29
27
36
34
32
30
28
26
25
48 47 46 45 44 43 42 41 40 39 38 37
MCLK
DSDB1
VD
SDIN1
TST
DSDA2
DSDA1
GND
SCLK
SDIN2
TST
LRCK(DSD_EN)
M3
(D
SD
_
S
C
L
K)
DS
DB
3
DS
DA
3
DS
DA
4
CS4382A
DS
DB
4
VL
S
SD
IN
4
M
2
(S
CL
/CCLK
)
M
1
(S
DA
/CDI
N)
VL
C
RS
T
FI
L
T
+
VQ
MU
TEC
2
AO
U
T
B4
-
AO
U
T
B4
+
M0
(A
D
0
/C
S
)
AOUTA2+
AOUTA2-
AO
U
T
B
1
+
AO
U
T
B
1
-
AO
U
T
A1
-
AO
U
T
A1
+
DS
D
B
2
MU
TE
C
1