Cirrus Logic CS4270 - Manual (Page 19)

DS686F1 19
CS4270
5. APPLICATIONS
5.1 Stand-Alone Mode
5.1.1 Access to Stand-Alone Mode
Reliable power-up is achieved by keeping the device in reset until the power supplies, clocks and config-
uration pins are stable. It is also recommended that RST be asserted if the analog or digital supplies drop
below the minimum specified operating voltages to prevent power glitch related issues.
The delay time from the release of reset until the device enters Stand-Alone Mode is 1,045 sample peri-
ods.
Table 2 lists the approximate wait time for each sampling mode.
5.1.2 Access to Master/Slave Mode
The CS4270 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated by the device. The LRCK
frequency is equal to Fs and the SCLK frequency is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.
SCLK must be 48x or 64x Fs to maximize system performance.
In Stand-Alone Mode, the CS4270 enters Slave Mode when SDOUT (M/S) is pulled low through a 47 k 
resistor. Master Mode is accessed by placing a 47 k  pull-up to VD on the SDOUT (M/S) pin.
Configuration of clock ratios in each of these modes is outlined in Table 4 .
5.1.3 System Clocking
The CS4270 operates at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes, as shown in
Table 3 .
Speed Mode Approximate Delay Time
Single-Speed 21.8 ms (48 kHz)
Double-Speed 10.9 ms (96 kHz)
Quad-Speed 5.4 ms (192 kHz)
Table 2. Approximate Delay Time from Release of RST to Entering Standalone Mode
Mode Sampling Frequency
Single-Speed 4-54 kHz
Double-Speed 50-108 kHz
Quad-Speed 100-216 kHz
Table 3. Speed Modes