Cirrus Logic CS4265 - Manual (Page 6)

6 DS657F3
CS4265
Figure 42.Consumer Output Circuit (VD = 5 V) ........................................................................................ 52
Figure 43.TTL/CMOS Output Circuit ......................................................................................................... 52
Figure 44.Channel Status Data Buffer Structure ....................................................................................... 53
Figure 45.Flowchart for Writing the E Buffer ............................................................................................. 54
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 24
Table 2. Common Clock Frequencies ....................................................................................................... 24
Table 3. MCLK Dividers ............................................................................................................................ 25
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 25
Table 5. Device Revision .......................................................................................................................... 36
Table 6. Freeze-able Bits .......................................................................................................................... 36
Table 7. DAC Digital Interface Formats .................................................................................................... 37
Table 8. De-Emphasis Control .................................................................................................................. 38
Table 9. Functional Mode Selection .......................................................................................................... 38
Table 10. ADC Digital Interface Formats .................................................................................................. 39
Table 11. MCLK Frequency ...................................................................................................................... 39
Table 12. DAC SDIN Source Selection ..................................................................................................... 40
Table 13. Example Gain and Attenuation Settings ................................................................................... 40
Table 14. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 41
Table 15. Analog Input Selection .............................................................................................................. 41
Table 16. Digital Volume Control Example Settings ................................................................................. 42
Table 17. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 43
Table 18. Transmitter Digital Interface Formats ........................................................................................ 45