Cirrus Logic CDB4245 - Manual (Page 5)

CDB4245
DS656DB1 5
1.6 FPGA
The FPGA handles both clock and data routing on the CDB4245. Clock and data routing selections made
via the CDB4245 Controls tab in the GUI will be handled by the FPGA with no user intervention required.
For advanced information regarding the internal registers and operation of the FPGA, see sections 5 and 6
beginning on page 11.
1.7 Canned Oscillators
Two canned oscillators, Y1 and Y2, are available to provide a master clock source to the CDB4245.
Each oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with
12.2880 MHz crystal oscillators populated.
1.8 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the headers J9, J10,
and J17.
The 8-pin, 2 row header, J10, provides access to the serial audio signals required to interface Serial Audio
Port 1 of the CS4245 with a DSP (see Figure 11 on page 24).
The 8-pin, 2 row header, J9, provides access to the serial audio signals required to interface Serial Audio
Port 2 of the CS4245 with a DSP (see Figure 11 on page 24).
The direction of the signals on headers J9 and J10 can be configured using the controls located within the
Board Controls group box on the CDB4245 Controls tab in the provided GUI software.
The 15-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I
2
C control signals by simply
removing all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable
to the “EXTERNAL CONTROL” position. A single “GND” row for the ribbon cable’s ground connection is pro-
vided to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user
choose to use the CDB for the I
2
C power rail.
1.9 Analog Inputs
RCA connectors supply the CS4245 analog inputs through single-ended, unity gain, active or passive cir-
cuits. Refer to the CS4245 data sheet for the ADC full-scale level.
A 4-pin CD-ROM type header is provided for easily connecting the analog outputs from a CD-ROM drive to
the analog inputs of the CS4245.
1.10 Analog Outputs
1.10.1 DAC Outputs
The CS4245 DAC analog outputs are routed through a single-pole passive RC filter. The output of the filter
is connected to RCA jacks for easy evaluation.
1.10.2 Auxiliary Outputs
The CS4245 auxiliary analog outputs are routed through a two-pole active filter. The output of the filter is
connected to RCA jacks for easy evaluation.
1.11 Serial Control Port
A graphical user interface is included with the CDB4245 to allow easy manipulation of the registers in the
CS4245, CS8416, CS8406, and FPGA. See the device-specific data sheets for the CS4245, CS8416, and
CD8406 internal register descriptions. The internal register map for the FPGA is located in section 5 on page
11.
Connecting a cable to the RS-232 connector (J42) and launching the Cirrus Logic FlexGUI software (Flex-
Loader.exe) will enable the CDB4245.
Refer to “PC Software Control” on page 7 for a description of the Graphical User Interface (GUI).