Cirrus Logic CDB4245 - Manual (Page 10)

CDB4245
10 DS656DB1
4.4.2 SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIF
Using the pre-configured script file named “SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIF.txt”,
an analog input signal applied to channel 1 of the CS4245 input multiplexer will be digitized by the ADC,
transmitted in S/PDIF format by the CS8406. A S/PDIF input signal will be converted to analog by the
CS4245 DAC and output through the passive output filter and RCA jacks. For proper operation of this script,
a valid S/PDIF signal must be applied.
The CS4245 is in synchronous mode, with the CS8416 as the source of MCLK for Clock Domain 1 and 2.
The CS8416 is also the sub-clock master to both the CS4245 Serial Audio Port 1 and 2, as well as the
CS8406.