Cirrus Logic CRD5376 - Manual (Page 4)

CRD5376
4 DS612RD2
3.4.7 Harmonics ........................................................................................................... 44
3.4.8 Spot Noise ........................................................................................................... 44
3.4.9 Plot Error ............................................................................................................. 44
3.5 Control Panel ................................................................................................................... 45
3.5.1 DF Registers ....................................................................................................... 46
3.5.2 DF Commands .................................................................................................... 46
3.5.3 SPI ...................................................................................................................... 46
3.5.4 Macros ................................................................................................................ 47
3.5.5 GPIO ................................................................................................................... 47
3.5.6 Customize ........................................................................................................... 48
3.5.7 External Macros .................................................................................................. 48
4. BILL OF MATERIALS ........................................................................................................... 49
5. LAYER PLOTS ...................................................................................................................... 51
6. SCHEMATICS ........................................................................................................................ 57
LIST OF FIGURES
Figure 1. CRD5376 Block Diagram ............................................................................................... 11
Figure 2. Differential Pair Routing ................................................................................................. 30
Figure 3. Quad Group Routing ...................................................................................................... 30
Figure 4. Bypass Capacitor Placement ......................................................................................... 31
LIST OF TABLES
Table 1. Amplifier Pin 13 Jumper Settings ...................................................................................... 6
Table 2. SDTKI Input Jumper Settings............................................................................................ 6
Table 3. PLL Clock Input Jumper Settings ...................................................................................... 6
Table 4. Pin Header Input Connections ........................................................................................ 12
Table 5. Analog Switch Settings.................................................................................................... 15
Table 6. Amplifier Pin 13 Jumper Settings .................................................................................... 16
Table 7. SDTKI Input Jumper Settings.......................................................................................... 22
Table 8. Clock Input / Output Jumper Settings.............................................................................. 25