Cirrus Logic CRD5376 - Manual (Page 21)

CRD5376
DS612RD2 21
The secondary serial port (SPI 2) and boundary scan JTAG port are unused on CRD5376.
2.3.1.1 MCLK vs. MCLK/2 Usage
The CS5376A digital filter creates the analog sampling clock used by the CS5372A ∆Σ modulators and
CS4373A test DAC. MCLK has strict jitter requirements to guarantee the accuracy of analog-to-digital and
digital-to-analog conversion, and so is carefully routed between the digital filter and modulators / test
DAC.
The CS3301A amplifier also requires an analog sampling clock to run the internal chopper stabilization
circuitry, but without the strict jitter or speed requirement as needed by the CS5372A
∆Σ modulators.
Therefore, the CS3301A amplifier can run equally well from the full-speed MCLK or half-speed MCLK/2.
Although MCLK could be used as the amplifier input clock, using MCLK/2 isolates the sensitive
modulator / test DAC analog sampling clock from the amplifier clock.
2.3.1.2 Configuration - SPI 1 Port
Configuration of the CS5376A digital filter is through the SPI 1 port by the on-board 8051 microcontroller
which receives commands from the PC evaluation software via the USB interface. Evaluation software
commands can write/read digital filter registers, specify digital filter coefficients and test bit stream data,
and start/stop digital filter operation.
How the digital filter receives configuration information, either from a microcontroller or configuration EE-
PROM, is selected by the BOOT signal. The BOOT signal is tied low on CRD5376 for microcontroller
configuration.
2.3.1.3 Digital Control Signals
The reset, synchronization and timebreak signals to the CS5376A digital filter are generated by the on-
board microcontroller and applied to the CS5376A digital filter RESET, SYNC, and TIMEB inputs.
Data collection transactions are initiated by a rising edge on the SDTKI input, as described in the
CS5376A data sheet. Two options for providing the required SDTKI rising edge are available on
SPI2 Signals Description
SCK2 Serial clock output (unused on CRD5376)
SO Serial data output (unused on CRD5376)
SI[1..4] Serial data inputs (unused on CRD5376)
JTAG Signals
Description
TRSTz JTAG reset (unused on CRD5376)
TMS JTAG test mode select (unused on CRD5376)
TCK JTAG test clock input (unused on CRD5376)
TDI JTAG test data input (unused on CRD5376)
TDO JTAG test data output (unused on CRD5376)