Cirrus Logic CRD5378 - Manual (Page 21)

CRD5378
DS639RD2 21
CS5378 PLL input frequency is specified at reset by the state of the GPIO[4..6]:PLL[0..2] pins, as detailed
in the CS5378 data sheet.
If no external system clock is supplied to CRD5378, the CRD5378 can select a PLL input clock from a
local oscillator. Using a clock divider, the on-board oscillator produces 1.024 MHz, 2.048 MHz, 4.096 MHz
and 32.768 MHz clock outputs that can be applied to the CS5378 CLK input.
.
Specification Value
Input Clock Frequency
1.024, 2.048, 4.096 MHz
Distributed Clock Synchronization ± 240 ns
Maximum Input Clock Jitter, RMS 1 ns
Specification Value
PLL Internal Clock Frequency
32.768 MHz
Maximum Jitter, RMS 300 ps
Loop Filter Architecture Internal
Specification Value
Oscillator - Citizen 32.768 MHz VCXO
CSX750VBEL32.768MTR
Surface Mount Package Type Leadless 6-Pin, 5x7 mm
Supply Voltage, Current 3.3 V, 11 mA
Frequency Stability, Pullability ± 50 ppm, ± 90 ppm
Startup Time 4 ms
Specification Value
Clock Divider - TI LittleLogic D-Flop
SN74LVC2G74DCTR
Surface Mount Package Type SSOP8-199
Supply Voltage, Current 3.3 V, 10
µA