Analog Devices ADSP-21020 - Manual (Page 17)

ADSP-21020
REV. C –17–
External Memory Three-State Control
K/B/T Grade K/B/T Grade B/T Grade K Grade
20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*
Parameter Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirement:
t
STS
xTS , Setup before CLKIN High 14 50 12 40 10 33 9 30 14 + DT/4 t
CK
ns
t
DADTS
xTS Delay after Address, Select 28 19 13 10 28 + 7DT/8 ns
t
DSTS
xTS Delay after XRD, XWR Low 16 11 7 6 16 + DT/2 ns
Switching Characteristic:
t
DTSD
Memory Interface Disable before
CLKIN High
0 –2 –4 –5 DT/4 ns
t
DTSAE
xTS High to Address, Select Enable 0 0 0 0 ns
NOTES
*DT = t
CK
– 50 ns.
xTS should only be asserted (low) during an active memory access cycle.
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Address = PMA23-0, DMA31-0. Select = PMS1-0, DMS3-0.
x = PM or DM.
CLKIN
ADDRESS,
SELECTS
t
STS
DATA
t
DTSD
t
DADTS
t
DTSAE
t
DSTS
t
STS
xRD, xWR
PMTS, DMTS
Figure 9. External Memory Three-State Control