Bus request/bus grant – Analog Devices ADSP-21020 User Manual
Page 16
ADSP-21020
REV. C
–16–
Bus Request/Bus Grant
K/B/T Grade K/B/T Grade B/T Grade
K Grade
20 MHz
25 MHz
30 MHz
33.3 MHz
Frequency Dependency*
Parameter
Min
Max
Min
Max Min Max
Min Max
Min
Max
Unit
Timing Requirement:
t
HBR
BR
Hold after CLKIN High
0
0
0
0
ns
t
SBR
BR
Setup before CLKIN High
18
15
13
12
18 + 5DT/16
ns
Switching Characteristic:
t
DMDBGL
Memory Interface Disable to BG Low –2
–2
–2
–2
ns
t
DME
CLKIN High to Memory Interface
Enable
25
20
16
15
25 + DT/2
ns
t
DBGL
CLKIN High to BG Low
22
22
22
22
ns
t
DBGH
CLKIN High to BG High
22
22
22
22
ns
NOTES
*DT = t
CK
– 50 ns.
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Buses are not granted until completion of current memory access.
See the Memory Interface chapter of the ADSP-21020 User’s Manual for BG, BR cycle relationships.
CLKIN
t
HBR
MEMORY
INTERFACE
t
SBR
t
DBGL
t
DMDBGL
t
HBR
t
SBR
t
DME
t
DBGH
BR
BG
Figure 8. Bus Request/Bus Grant