Asus A8N32-SLI User Manual
Page 22
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C h a p t e r 1 : P r o d u c t i n t r o d u c t i o n
C h a p t e r 1 : P r o d u c t i n t r o d u c t i o n
C h a p t e r 1 : P r o d u c t i n t r o d u c t i o n
C h a p t e r 1 : P r o d u c t i n t r o d u c t i o n
C h a p t e r 1 : P r o d u c t i n t r o d u c t i o n
Precision Tweaker
Precision Tweaker
Precision Tweaker
Precision Tweaker
Precision Tweaker
This feature allows you to fine tune the CPU/memory voltage and gradually
increase the memory Front Side Bus (FSB) and PCI Express frequency at
1MHz increment to achieve maximum system performance.
PEG Link Mode for two graphics cards
PEG Link Mode for two graphics cards
PEG Link Mode for two graphics cards
PEG Link Mode for two graphics cards
PEG Link Mode for two graphics cards
This feature enhances your PCI Express graphics card performance. It allows
the motherboard to automatically adjust the PCI Express graphics link mode
to the correct frequency based on the system configuration. Four
additional settings are available for overclocking the PEG Link Mode. See
page 4-22 for details.
AI NET
AI NET
AI NET
AI NET
AI NET
AI NET is a BIOS-based diagnostic tool that detects and reports Ethernet
cable faults and shorts. With this utility, you can easily monitor the
condition of the Ethernet cable(s) connected to the Marvell
®
LAN (RJ-45)
port.
ASUS Two-slot thermal design
ASUS Two-slot thermal design
ASUS Two-slot thermal design
ASUS Two-slot thermal design
ASUS Two-slot thermal design
The motherboard is designed with two PCI slots placed between the PCI
Express x16 slots, allowing increased airflow between the two PCI Express
x16 graphics cards. This special design permits more room for ventilation,
thus lowering the overall system temperature.
CrashFree BIOS 2
CrashFree BIOS 2
CrashFree BIOS 2
CrashFree BIOS 2
CrashFree BIOS 2
This feature allows you to restore the original BIOS data from the support CD
in case when the BIOS codes and data are corrupted. This protection
eliminates the need to buy a replacement ROM chip. See page 4-5 for details.