ARM VERSION 1.2 - Manual (Page 196)

Thumb Instruction Reference
5-2 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
Table 5-1 Location of Thumb instructions and pseudo-instructions
Instruction mnemonic Brief description Page Architecture a
ADC Add with carry page 5-21 4T
ADD Add page 5-15 4T
ADR Load address (pseudo-instruction) page 5-40 -
AND Logical AND page 5-23 4T
ASR Arithmetic shift right page 5-24 4T
B Branch page 5-32 4T
BIC Bit clear page 5-23 4T
BKPT Breakpoint page 5-38 5T
BL Branch with link page 5-34 4T
BLX Branch with link and exchange instruction sets page 5-36 5T
BX Branch and exchange instruction sets page 5-35 4T
CMN , CMP Compare negative, Compare page 5-26 4T
EOR Logical exclusive OR page 5-23 4T
LDMIA Load multiple registers, increment after page 5-13 4T
LDR Load register, immediate offset page 5-5 4T
LDR Load register, register offset page 5-7 4T
LDR Load register, pc or sp relative page 5-9 4T
LDR Load register (pseudo-instruction) page 5-41 -
LSL , LSR Logical shift left, Logical shift right page 5-24 4T
MOV Move page 5-28 4T
MUL Multiply page 5-21 4T
MVN , NEG Move NOT, Negate page 5-28 4T
NOP No operation (pseudo-instruction) page 5-43 -
ORR Logical OR page 5-23 4T
POP , PUSH Pop registers from stack, Push registers onto stack page 5-11 4T