ARM VERSION 1.2 - Manual (Page 134)

ARM Instruction Reference
4-24 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.3.1 Flexible second operand
Most ARM general data processing instructions have a flexible second operand. This is
shown as
Operand2 in the descriptions of the syntax of each instruction.
Syntax
Operand2 has two possible forms:
#immed_8r
Rm{, shift}
where:
immed_8r is an expression evaluating to a numeric constant. The constant must
correspond to an 8-bit pattern rotated by an even number of bits within a
32-bit word (but see Instruction substitution on page 4-26).
Rm is the ARM register holding the data for the second operand. The bit
pattern in the register can be shifted or rotated in various ways.
shift is an optional shift to be applied to Rm . It can be any one of:
ASR n
arithmetic shift right n bits. 1 ≤
n
≤ 32.
LSL n
logical shift left n bits. 0
≤
n
≤ 31.
LSR n
logical shift right n bits. 1
≤
n
≤ 32.
ROR n
rotate right n bits. 1 ≤
n
≤ 31.
RRX rotate right one bit, with extend.
type Rs where:
type is one of ASR , LSL , LSR , ROR .
Rs is an ARM register supplying the shift amount.
Only the least significant byte is used.
Note
The result of the shift operation is used as Operand2 in the instruction, but
Rm itself is not altered.