ARM VERSION 1.2 - Manual (Page 113)

ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 4-3
MUL Multiply page 4-40 2
MVN Move not page 4-32 All
ORR Logical OR page 4-30 All
PLD Cache preload page 4-20 5E d
QADD , QDADD , QDSUB , QSUB Saturating arithmetic page 4-55 5ExP e
RSB , RSC , SBC Reverse sub, Reverse sub with carry, Sub with carry page 4-27 All
SMLAL Signed multiply-accumulate (64 <= 32 x 32 + 64) page 4-42 M f
SMLALxy Signed multiply-accumulate (64 <= 16 x 16 + 64) page 4-51 5ExP e
SMLAWy Signed multiply-accumulate (32 <= 32 x 16 + 32) page 4-49 5ExP e
SMLAxy Signed multiply-accumulate (32 <= 16 x 16 + 32) page 4-46 5ExP e
SMULL Signed multiply (64 <= 32 x 32) page 4-42 M f
SMULWy Signed multiply (32 <= 32 x 16) page 4-48 5ExP e
SMULxy Signed multiply (32 <= 16 x 16) page 4-44 5ExP e
STC , STC2 Store coprocessor page 4-67 2, 5ExP e
STM Store multiple registers page 4-18 All
STR Store register page 4-6 All
SUB Subtract page 4-27 All
SWI Software interrupt page 4-72 All
SWP Swap registers and memory page 4-22 3
TEQ , TST Test equivalence, Test page 4-36 All
UMLAL , UMULL Unsigned MLA, MUL (64 <= 32 x 32 (+ 64)) page 4-42 M f
a. n : available in ARM architecture version n and above
b. nT : available in T variants of ARM architecture version n and above
c. XScale: XScale coprocessor instructions
d. nE : available in E variants of ARM architecture version n and above, except ExP variants
e. nE : available in all E variants of ARM architecture version n and above, including ExP variants
f.
M : available in ARM architecture version 3M, and 4 and above, except xM versions
Table 4-1 Location of ARM instructions (continued)
Mnemonic Brief description Page Architecture a