Acer Altos R920 Series - Manual (Page 183)

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Introduction
The system’s memory architecture supports up to four memory boards
organized by branches and channels. The MCH (memory controller
hub) on the north bridge has two branches with branch 0 going to
channels 0 and 1 or memory board A and B, and branch 1 to channels 2
and 3 or memory board C and D.
In dual-channel mode, FBDIMMs on adjacent channels work in lockstep
to provide the same cache line data and a combined ECC. In the single-
channel mode only channel 0 is active. The BIOS dynamically configures
the memory controller in accordance with the available FBDIMM
population and the selected RAS (reliability, availability, serviceability
(RAS) mode operation.