PNI RM3000-F Sensor Suite - Manual (Page 39)

PNI Sensor Corporation Doc #1016102 r04
RM3000-f & RM2000-f Sensor Suite User Manual Page 39
The SSN input may be returned HIGH at this point to free up host communication
with another device if desired. This will not affect the measurement process.
A measurement is taken, which consists of forward biasing the sensor and making
a period count; then reverse biasing the sensor and counting again; and then
taking the difference between the two directions and presenting this value.
At the end of the measurement, the DRDY pin is set HIGH, indicating data is
ready, and the 3D MagIC is placed in Idle Mode.
The SSN input should be set LOW, if it is not already, to read the data.
The data is clocked out on the MISO pin with the next 16 clock cycles.
If another measurement is to be made immediately, the SSN pin can remain low and the
process repeated. Otherwise, it generally is recommended to set the SSN pin HIGH to
release the SPI serial bus.
6.2 Enhanced Legacy Operation
Note: Enhanced Legacy Operation involves improving performance of a legacy system by
implementing only software changes. If the user can make both software and hardware changes,
then operation in Standard Mode is recommended as it allows for multi-axis measurement operation
and finer granularity in establishing the number of cycle counts.
The 3D MagIC incorporates a Clock Divide Register that effectively divides the 3D MagIC’s
high-speed internal clock by some integer value (Clock Divide Value). In Legacy Mode the
default is 16 as this results in performance matching that of the 11096 ASIC at similar Period
Select values. But for the most efficient operation, the value should be 1 since this gives the
greatest time-based sensitivity. If a legacy user cannot set pin #12 to DVSS to operate in
Standard Mode, but can make code changes, it is possible to significantly reduce power
consumption (see Table 6-4) by over-writing the Legacy Mode default Clock Divide Value
and using a smaller Period Select value. In this case, the user first will write to the Clock
Divide Register and after this follow the same process as for Legacy Operation, except with a
different Period Select value.
For example, if a user operates in default Legacy Mode and sets the Period Select value to 5,
the cycle count will be 1024 and the effective clock speed with be ~2.8 MHz. By changing
the Clock Divide value from 16 (Legacy Mode default) to 1, the effective clock speed
increases to ~45 MHz. With this significantly higher clock speed, the Period Select value
can be reduced to 1 (64 cycle counts) such that the gain remains unchanged but the time to
take the measurement, and hence power consumption, is dramatically reduced.