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Doc 1017252 r02
RM3100 Evaluation Board User Manual
Page 2 of 33
List of Figures
Figure 3-1: RM3100 Evaluation Board Mechanical Drawing ................................................... 7
Figure 4-1: SPI Timing Diagram, CPOL = CPHA = 0 ............................................................. 13
Figure 4-2: SPI Timing Diagram, CPOL = CPHA = 1 ............................................................. 13
Figure 5-1: SPI Activity Sequence Diagram ........................................................................... 28
List of Tables
Table 3-1: Operating Performance ........................................................................................... 5
Table 3-2: Absolute Maximum Ratings .................................................................................... 6
Table 3-3: Operating Conditions............................................................................................... 6
Table 4-1: RM3100 Evaluation Board Pin Assignments .......................................................... 9
Table 4-2: SPI Timing Specifications ..................................................................................... 14
Table 5-1: RM3100 Evaluation Board Register Map .............................................................. 16
Table 5-2: Cycle Count Registers ........................................................................................... 17
Table 5-3: Continuous Mode DRDY Options ......................................................................... 19
Table 5-4: CMM Update Rates ............................................................................................... 20
Table 5-5: Alarm Lower and Upper Limit Registers ............................................................... 21
Table 5-6: Alarm Hysteresis Registers ................................................................................... 22
Table 5-7: Absolute vs. Relative Alarm Mode Example ......................................................... 23
Table 5-8: Measurement Results Registers ........................................................................... 25
Table 5-9: BIST Timeout Period ............................................................................................. 26
Table 5-10: BIST LR Periods .................................................................................................. 26