Advantech PCI-1710 - Manual (Page 59)

Appendix A 8524 Counter Chip Functions 55
becomes:
BASE + 30(Dec) 82C54 control, read-back mode
Bit
D7 D6 D5 D4 D3 D2 D1 D0
Value 1 1 CNT STA C2 C1 C0 X
CNT = 0 Latch count of selected counter(s).
STA = 0 Latch status of selected counter(s).
C2, C1 & C0 Select counter for a read-back operation.
C2 = 1 select Counter 2
C1 = 1 select Counter 1
C0 = 1 select Counter 0
If you set both SC1 and SC0 to 1 and STA to 0, the register selected
by C2 to C0 contains a byte which shows the status of the counter.
The data format of the counter read/write register then becomes:
BASE+24/26/28(Dec) Status read-back mode
Bit D7 D6 D5 D4 D3 D2 D1 D0
Value OUT NC RW1 RW0 M2 M1 M0 BCD
OUT Current state of counter output
NC Null count is 1 when the last count written to the counter
register has been loaded into the counting element