Advantech PCI-1710 - Manual (Page 44)

40 PCI-1710/1710HG User's Manual
GATE External trigger gate function enable bit
Set 1 to enable external trigger gate function, and set 0 to disable.
IRQEN Interrupt enable bit
Set 1 to enable interrupt, and set 0 to disable.
ONE/FH Interrupt source bit
Set 0 to interrupt when an A/D conversion occurs, and set 1 to
interrupt when the FIFO is half full.
CNT0 Counter 0 clock source select bit
0 means that the clock source of Counter 0 comes from the internal
clock (100 kHz), and 1 means that the clock source of Counter 0
comes from the external clock (maximum up to 10 MHz).
4.8 Status Register — BASE+6 and
BASE+7
The registers of BASE+6 and BASE+7 provide information for the A/
D configuration and operation.
Table 4-8: Status register
The content of the status register of BASE+6 is the same as that of the
control register.
F/E FIFO Empty flag
This bit indicates whether the FIFO is empty. 1 means that the FIFO is
empty.
Read Status Register
Bit # 7 6 5 4 3 2 1 0
BASE+7 IRQ F/F F/H F/E
BASE+6 CNT0 ONE/FH IRQEN GATE EXT PACER SW