Advantech PCI-1710 - Manual (Page 45)

Chapter 4 Register Structure and Format 41
F/H FIFO Half-full flag
This bit indicates whether the FIFO is half-full. 1 means that the FIFO
is half-full.
F/F FIFO Full flag
This bit indicates whether the FIFO is full. 1 means that the FIFO is
full.
IRQ Interrupt flag
This bit indicates the interrupt status. 1 means that an interrupt has
occurred.
4.9 Clear Interrupt and FIFO — BASE+8
and BASE+9
Writing data to either of these two bytes clears the interrupt or the
FIFO.
Table 4-9: Registers to clear interrupt and FIFO
Write Clear Interrupt and FIFO
Bit # 7 6 5 4 3 2 1 0
BASE+9 Clear FIFO
BASE+8 Clear Interrupt