2 chipset, Chipset -15, Chipset – Asus P5QL/EPU User Manual
Page 53: Intel(r).speedstep(tm).tech.[enabled, Intel(r).c-state.tech.[enabled, Dram.timing.control.[auto, Execute-disable.bit.capability.[enabled
ASUS P5QL/EPU
2-15
The following item appears only when you installed an Intel
®
Pentium
®
4 or later CPU that
supports the Enhanced Intel
®
SpeedStep
®
Technology (EIST).
Intel(R).SpeedStep(TM).Tech.[Enabled]
Allows you to use the Enhanced Intel
®
SpeedStep
®
Technology. When set to [Enabled], you
can adjust the system power settings in the operating system to use the EIST feature. Set
this item to [Disabled] if you do not want to use the EIST.
Configuration options: [Enabled] [Disabled]
Intel(R).C-STATE.Tech.[Enabled]
Allows you enable or disable the Intel
®
C-STATE Technology. When enabled, the CPU idle is
set to C2/C3/C4. Configuration options: [Disabled] [Enabled]
2.5.2.
Chipset
The Chipset menu allows you to change the advanced chipset settings. Select an item then
press
North Bridge Configuration
Memory.Remap.Feature.[Enabled]
Allows you to enabled or disable the remapping of the overlapped PCI memory above the
total physical memory. Enable this option only when you install 64-bit operating system.
Configuration options: [Disabled] [Enabled]
Memory.Hole.[Disabled]
Allows you to configure the memory hole. Configuration options: [Disabled] [15MB-16MB]
DRAM.Timing.Control.[Auto]
Allows you to configure the DRAM timing control. Configuration options: [Auto] [Manual]
Execute-Disable.Bit.Capability.[Enabled]
Allows you to enable or disable the No-Execution Page Protection Technology. Setting this
item to [Disabled] forces the XD feature flag to always return to zero (0).
Configuration options: [Disabled] [Enabled]
The follow items appear only when you set the [DRAM.Timing.Control] item to [Manual].
CAS# Latency [5 DRAM Clocks]
Controls the latency between the SDRAM read command and the time the data
actually becomes available. Configuration options: [3 DRAM Clock] [4 DRAM Clocks]
[5 DRAM Clocks] ~ [11 DRAM Clocks].
DRAM RAS# to CAS# Delay [5 DRAM Clocks]
Configuration options: [3 DRAM Clocks] [4 DRAM Clocks] ~ [18 DRAM Clocks].
DRAM RAS# Precharge [5 DRAM Clocks]
Configuration options: [3 DRAM Clocks] [4 DRAM Clocks] ~ [18 DRAM Clocks].
RAS# Activate to Precharge [15 DRAM Clocks]
Configuration options: [3 DRAM Clocks] [4 DRAM Clocks] ~ [34 DRAM Clocks].