Rainbow Electronics LM63 - Manual (Page 6)

SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
DD
= +3.0 VDC to +3.6 VDC, C
L
(load capacitance) on output lines =
80 pF. Boldface limits apply for T
A
= T
J
; T
MIN
≤ T
A
≤ T
MAX
; all other limits T
A
= T
J
= +25˚C, unless otherwise noted. The
switching characteristics of the LM63 fully meet or exceed the published specifications of the SMBus version 2.0. The following
parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM63. They adhere to but are
not necessarily the same as the SMBus bus specifications.
Symbol Parameter Conditions
Limits
(Note 8)
Units
(Limit)
f
SMB
SMBus Clock Frequency 10
100
kHz (min)
kHz (max)
t
LOW
SMBus Clock Low Time From V
IN(0) max
to V
IN(0) max
4.7 µs (min)
t
HIGH
SMBus Clock High Time From V
IN(1) min
to V
IN(1) min
4.0
50
µs (min)
µs (max)
t
R
SMBus Rise Time (Note 11) 1 µs (max)
t
F
SMBus Fall Time (Note 12) 0.3 µs (max)
t
OF
Output Fall Time C
L
= 400 pF, I
O
= 3 mA 250 ns (max)
t
TIMEOUT
SMBData and SMBCLK Time Low for Reset
of Serial Interface See (Note 13)
25
35
ms (min)
ms (max)
t
SU:DAT
Data In Setup Time to SMBCLK High 250 ns (min)
t
HD:DAT
Data Out Hold Time after SMBCLK Low 300
930
ns (min)
ns (max)
t
HD:STA
Hold Time after (Repeated) Start Condition.
After this period the first clock is generated.
4.0 µs (min)
t
SU:STO
Stop Condition SMBCLK High to SMBDAT
Low (Stop Condition Setup)
100 ns (min)
t
SU:STA
SMBus Repeated Start-Condition Setup Time,
SMBCLK High to SMBDAT Low
4.7 µs (min)
t
BUF
SMBus Free Time between Stop and Start
Conditions
4.7 µs (min)
20057004
SMBus Timing Diagram for SMBCLK and SMBDAT Signals
LM63
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