Rainbow Electronics MAX1813 User Manual
Page 27
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
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27
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation specifications often limits how small
the MOSFET can be. Again, the optimum occurs when
the switching losses equal the conduction (R
DS(ON)
)
losses. High-side switching losses don’t usually
become an issue until the input is greater than approxi-
mately 15V.
Calculating the power dissipation in the high-side MOS-
FET (Q
H
) due to switching losses is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PC board layout charac-
teristics. The following switching-loss calculation
provides only a very rough estimate and is no substi-
tute for breadboard evaluation, preferably including
verification using a thermocouple mounted on Q1:
where C
RSS
is the reverse transfer capacitance of Q
H
,
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC-adapter
voltages are applied, due to the squared term in the C
x V
IN2
x ƒ
SW
switching-loss equation. If the high-side
MOSFET chosen for adequate R
DS(ON)
at low battery
voltages becomes extraordinarily hot when biased from
V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (Q
L
), the worst-case power
dissipation always occurs at the maximum input
voltage:
The worst case MOSFET power dissipation occurs
under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
where I
LIMIT(HIGH)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/3 of the load current. This diode is optional and
can be removed if efficiency isn’t critical.
Setting Voltage Positioning
Voltage positioning dynamically changes the output
voltage set point in response to the load current. When
the output is loaded, the signal fed back from the VPCS
input adjusts the output voltage set point, thereby
decreasing power dissipation. The load-transient
response of this control loop is extremely fast yet well
controlled, so the amount of voltage change can be
accurately confined within the limits stipulated in the
microprocessor power-supply guidelines. To under-
stand the benefits of dynamically adjusting the output
voltage, see Voltage Positioning and Effective
Efficiency.
The amount of output voltage change is adjusted by an
external gain resistor (R
AVPS
). Place R
AVPS
between
REF and CC (Figure 8). The voltage developed across
the current-sense resistor (V
VPCS
) relates to the output
voltage as follows:
where V
OUT(PROG)
is the programmed output voltage
set by the DAC code (Table 5), and the VPCS transcon-
ductance (G
m
) is typically 20µS (see Electrical
Characteristics). The MAX1813 contains internal
clamps to limit the voltage positioning between 10%
below and 2% above the programmed output voltage.
The MAX1813 determines the load current from the
voltage across the current-sense resistor (R
SENSE
)
between the source of the low-side MOSFET and
PGND. Therefore, the current-sense voltage present at
VPCS is determined by:
V
= -I
R
(1-D)
VPCS
LOAD SENSE
V
= V
1+
G R
V
V
OUT
OUT(PROG)
m AVPS VPCS
REF
I
= I
+
I
LIR
2
LOAD
LIMIT(HIGH)
LOAD(MAX)
PD Q
sistive
L
(
Re
)
=
1-
V
V
I
R
OUT
IN(MAX)
LOAD
2
DS(ON)
PD Q
Switching
H
SW
(
)
=
ƒ
V
C
I
I
IN(MAX)
2
RSS
LOAD
GATE
PD Q
sistive
H
(
Re
)
=
V
I
R
V
OUT LOAD
2
DS(ON)
IN