Table 1. control register addressing, Serial digital interface, Applications information – Rainbow Electronics MAX1401 User Manual

Page 14: Modulator data output

MAX1401

+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC

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Serial Digital Interface

The serial digital interface provides access to eight on-
chip registers (Figure 3). All serial-interface commands
begin with a write to the communications register
(COMM). On power-up, system reset, or interface reset,
the part expects a write to its communications register.
The COMM register access begins with a 0 start bit.
The COMM register R/W bit selects a read or write
operation, and the register select bits (RS2, RS1, RS0)
select the register to be addressed. Hold DIN high
when not writing to COMM or another register (Table 1).

The serial interface consists of five signals: CS, SCLK,
DIN, DOUT, and INT. Clock pulses on SCLK shift bits
into DIN and out of DOUT. INT provides an indication
that data is available. CS is a device chip-select input
as well as a clock polarity select input (Figure 4).

Using CS allows the SCLK, DIN, and DOUT signals to be
shared among several SPI-compatible devices. When
short on I/O pins, connect CS low and operate the serial
digital interface in CPOL = 1, CPHA = 1 mode using
SCLK, DIN, and DOUT. This 3-wire interface mode is
ideal for opto-isolated applications. Furthermore, a
microcontroller (such as a PIC16C54 or 80C51) can use
a single bidirectional I/O pin for both sending to DIN and
receiving from DOUT (see

Applications Information

because the MAX1401 drives DOUT only during a read
cycle.

Additionally, connecting the INT signal to a hardware
interrupt allows faster throughput and reliable, collision-
free data flow.

The MAX1401 features a mode where the raw modula-
tor data output is accessible. In this mode the DOUT
and INT functions are reassigned (see the

Modulator

Data Output

section).

DATA REGISTER D1–D0/CID

RS0

GLOBAL SETUP REGISTER 1

GLOBAL SETUP REGISTER 2

SPECIAL FUNCTION REGISTER

XFER FUNCTION REGISTER 1

XFER FUNCTION REGISTER 2

XFER FUNCTION REGISTER 3

DATA REGISTER D17–D10

DATA REGISTER D9–D2

COMMUNICATIONS REGISTER

RS1

RS2

DIN

DOUT

SELECT

DECODER

Figure 3. Register Summary

DIN

(DURING

WRITE)*

DOUT

(DURING

READ)*

MSB D6

INT

SCLK

(CPOL = 1)

SCLK

(CPOL = 0)

*DOUT IS HIGH IMPEDANCE DURING THE WRITE CYCLE; DIN IS IGNORED
DURING THE READ CYCLE.