Rainbow Electronics MAX1718 - Manual (Page 27)

MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
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power-dissipation limits often limits how small the MOS-
FET can be.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
2 f
SW
switching-loss equation. If the high-side MOS-
FET you’ve chosen for adequate R DS(ON) at low battery
voltages becomes extraordinarily hot when subjected
to V
IN(MAX) , reconsider your choice of MOSFET.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induc-
tance, and PC board layout characteristics. The following
switching-loss calculation provides only a very rough
estimate and is no substitute for breadboard evaluation
and temperature measurements:
where C RSS is the reverse transfer capacitance of Q1
and I GATE is the peak gate-drive source/sink current
(2A typ).
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:
For both Q1 and Q2, note the MOSFET’s maximum
junction temperature and the thermal resistance that
will be realistically achieved with the device packaging
and your thermal environment to avoid overheating.
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
I LOAD = I LIMIT(HIGH) + (LIR / 2) ✕ I LOAD(MAX)
where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
normal I
LOAD value can be used for calculating compo-
nent stresses.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency isn’t critical.
Applications Information
Voltage Positioning
Powering new mobile processors requires new tech-
niques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
allows a larger step down when the output current sud-
denly increases, and regulating at the lower output volt-
age under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitor’s ESR can be increased.
Adding a series output resistor positions the full-load
output voltage below the actual DAC programmed volt-
age. Connect FB directly to the inductor side of the volt-
age-positioning resistor (R8, 4m
Ω). The other side of
the voltage-positioning resistor should be connected
directly to the output filter capacitor with a short, wide
PC board trace. With a 20A full-load current, R8 causes
an 80mV drop. This 80mV is a -6.4% droop.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in R8.
For a nominal 1.25V, 20A output, reducing the output
voltage 6.4% gives an output voltage of 1.17V and an
output current of 18.7A. Given these values, CPU
power consumption is reduced from 25W to 21.9W. The
additional power consumption of R8 is:
4m Ω ✕ 18.7A 2 = 1.4W
And the overall power savings is as follows:
25 - (21.9 + 1.4) = 1.7W
In effect, 3W of CPU dissipation is saved, and the
power supply dissipates some of the power savings,
but both the net savings and the transfer of dissipation
away from the hot CPU are beneficial.
Reduced-Power-Dissipation
Voltage Positioning
A key benefit of voltage positioning is reduced power
dissipation, especially at heavy loads. In the standard
PD Q
V
V
I R
OUT
IN MAX
LOAD DS ON
( )
( )
( )
2 1
2 = −






×
PD Q Switching
C V f I
I
RSS IN MAX SW LOAD
GATE
( )
( )
1
2
=
Ч Ч Ч