Rainbow Electronics ADC1175-50 - Manual (Page 3)

Pin Descriptions and Equivalent Circuits
(LLP pins in parentheses) (Continued)
Pin
No.
Symbol Equivalent Circuit Description
17
(15)
V
RT
Analog input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AV
DD
, optimized value of 2.6V. Voltages on V
RT
and V
RB
inputs define the V
IN
conversion range.
Bypass well. See Section 2.0 for more information.
23
(21)
V
RB
Analog input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0.0V
to 4.0V, with optimized value of 0.6V. Voltage on
V
RT
and V
RB
inputs define the V
IN
conversion
range. Bypass well. See Section 2.0 for more
information.
22
(20)
V
RBS
Reference Bottom Bias with internal pull down
resistor. Short to V
RB
to self-bias the reference
ladder. Bypass well if not grounded. See Section
2.0 for more information.
1
(23)
PD
CMOS/TTL compatible Digital input that, when high,
puts the ADC1175-50 into a power-down mode
where total power consumption is typically less than
5 mW. With this pin low, the device is in the normal
operating mode.
12
(10)
CLK
CMOS/TTL compatible digital clock input. V
IN
is
sampled on the falling edge of CLK input.
3 thru
10
(1 thru
8)
D0–D7
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are in a
high impedance mode when the PD pin is low.
ADC1
175-50
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