Rainbow Electronics ADC1175-50 - Manual (Page 15)

Applications Information
(All Schematic
pin numbers refer to the TSSOP.) (Continued)
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal.
8.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 50 mV below the ground pins or 50 mV above the
supply pins. Exceeding these limits on even a transient basis
may cause faulty or erratic operation. It is not uncommon for
high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground.
A resistor of about 50
Ω
to 100
Ω
in series with the offending
digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC1175-50. Such practice may lead to conversion inaccu-
racies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is
required from DV
DD
and DGND. These large charging cur-
rent spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74ACQ541, for example) may be necessary if the data bus
to be driven is heavily loaded. Dynamic performance can
also be improved by adding 47
Ω
series resistors at each
digital output, reducing the energy coupled back into the
converter output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the capacitance seen at the
input alternates between 4 pF and 7 pF with the clock. This
dynamic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device. The CLC409 has been found to be an excel-
lent device for driving the ADC1175-50.
Driving the V
RT
pin or the V
RB
pin with devices that can
not source or sink the current required by the ladder. As
mentioned in Section 2.0, care should be taken to see that
any driving devices can source sufficient current into the V
RT
pin and sink sufficient current from the V
RB
pin. If these pins
are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. Simple gates with RC
timing is generally inadequate as a clock source.
Input test signal contains harmonic distortion that inter-
feres with the measurement of dynamic signal to noise
ratio. Harmonic and other interfering signals can be re-
moved by inserting a filter at the signal input. Suitable filters
are shown in
Figure 8 and Figure 9. The circuit of Figure 8
has a cutoff of about 5.5 MHz and is suitable for input
frequencies of 1 MHz to 5 MHz. The circuit of
Figure 9 has a
cutoff of about 11 MHz and is suitable for input frequencies
of 5 MHz to 10 MHz. These filters should be driven by a
generator of 75
Ω
source impedance and terminated with a
75 Ω resistor.
Not considering the effect on a driven CMOS digital
circuit(s) when the ADC1175-50 is in the power down
mode. Because the ADC1175 output goes into a high im-
pedance state when in the power down mode, any CMOS
device connected to these outputs will have their inputs
floating. Should the inputs float to a level near 2.5V, the
CMOS device could exhibit relative large currents through its
input stage. The solution is to use pull-down resistors. The
value of these resistors is not critical, as long as they do not
cause excessive currents in the outputs of the ADC1175-50.
These currents could result in degraded SNR and SINAD
performance of the ADC1175-50. Values between 5 k
Ω and
100 k Ω should work well.
DS100896-29
FIGURE 7. Isolating the ADC Clock from Digital
Circuitry
DS100896-30
FIGURE 8. 5.5 MHz Low Pass filter to eliminate harmonics at the signal input. Use at input frequencies of 1 MHz to 5
MHz.
ADC1
175-50
www.national.com 15