Rainbow Electronics ATmega32L User Manual

Features

Table of contents

Document Outline

Features
Pin Configurations
Disclaimer
Overview
- Block Diagram
- Pin Descriptions
About Code Examples
AVR CPU Core
- Introduction
- Architectural Overview
- ALU – Arithmetic Logic Unit
- Status Register
- General Purpose Register File
  - The X-register, Y-register and Z-register
- Stack Pointer
- Instruction Execution Timing
- Reset and Interrupt Handling
  - Interrupt Response Time
AVR ATmega32 Memories
- In-System Reprogrammable Flash Program Memory
- SRAM Data Memory
  - Data Memory Access Times
- EEPROM Data Memory
- I/O Memory
System Clock and Clock Options
- Clock Systems and their Distribution
- Clock Sources
- Default Clock Source
- Crystal Oscillator
- Low-frequency Crystal Oscillator
- External RC Oscillator
- Calibrated Internal RC Oscillator
  - Oscillator Calibration Register – OSCCAL
- External Clock
- Timer/Counter Oscillator
Power Management and Sleep Modes
- MCU Control Register – MCUCR
- Idle Mode
- ADC Noise Reduction Mode
- Power-down Mode
- Power-save Mode
- Standby Mode
- Extended Standby Mode
- Minimizing Power Consumption
System Control and Reset
- Resetting the AVR
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Control and Status Register – MCUCSR
- Internal Voltage Reference
  - Voltage Reference Enable Signals and Start-up Time
- Watchdog Timer
  - Watchdog Timer Control Register – WDTCR
Interrupts
- Interrupt Vectors in ATmega32
  - Moving Interrupts Between Application and Boot Space
  - General Interrupt Control Register – GICR
I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
External Interrupts
- MCU Control Register – MCUCR
- MCU Control and Status Register – MCUCSR
- General Interrupt Control Register – GICR
- General Interrupt Flag Register – GIFR
8-bit Timer/Counter0 with PWM
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
Timer/Counter0 and Timer/Counter1 Prescalers
- Internal Clock Source
- Prescaler Reset
- External Clock Source
- Special Function IO Register – SFIOR
16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
  - Reusing the Temporary High Byte Register
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
- Asynchronous Operation of the Timer/Counter
- Timer/Counter Prescaler
  - Special Function IO Register – SFIOR
Serial Peripheral Interface – SPI
- SS Pin Functionality
- Data Modes
USART
- Overview
  - AVR USART vs. AVR UART – Compatibility
- Clock Generation
- Frame Formats
  - Parity Bit Calculation
- USART Initialization
- Data Transmission – The USART Transmitter
- Data Reception – The USART Receiver
- Asynchronous Data Reception
- Multi-processor Communication Mode
  - Using MPCM
- Accessing UBRRH/ UCSRC Registers
  - Write Access
  - Read Access
- USART Register Description
- Examples of Baud Rate Setting
Two-wire Serial Interface
- Features
- Two-wire Serial Interface Bus Definition
  - TWI Terminology
  - Electrical Interconnection
- Data Transfer and Frame Format
- Multi-master Bus Systems, Arbitration and Synchronization
- Overview of the TWI Module
- TWI register description
- Using the TWI
- Transmission Modes
- Multi-master Systems and Arbitration
Analog Comparator
- Special Function IO Register – SFIOR
- Analog Comparator Control and Status Register – ACSR
- Analog Comparator Multiplexed Input
Analog to Digital Converter
- Features
- Operation
- Starting a Conversion
- Prescaling and Conversion Timing
  - Differential Gain Channels
- Changing Channel or Reference Selection
  - ADC Input Channels
  - ADC Voltage Reference
- ADC Noise Canceler
- ADC Conversion Result
JTAG Interface and On-chip Debug System
- Features
- Overview
- Test Access Port – TAP
- TAP Controller
- Using the Boundary- scan Chain
- Using the On-chip Debug System
- On-chip Debug Specific JTAG Instructions
- On-chip Debug Related Register in I/O Memory
  - On-chip Debug Register – OCDR
- Using the JTAG Programming Capabilities
- Bibliography
IEEE 1149.1 (JTAG) Boundary-scan
- Features
- System Overview
- Data Registers
- Boundary-scan Specific JTAG Instructions
- Boundary-scan Chain
- ATmega32 Boundary- scan Order
- Boundary-scan Description Language Files
Boot Loader Support – Read-While-Write Self-Programming
- Features
- Application and Boot Loader Flash Sections
  - Application Section
  - BLS – Boot Loader Section
- Read-While-Write and no Read-While-Write Flash Sections
  - RWW – Read-While-Write Section
  - NRWW – No Read-While-Write Section
- Boot Loader Lock Bits
- Entering the Boot Loader Program
  - Store Program Memory Control Register – SPMCR
- Addressing the Flash during Self- Programming
- Self-Programming the Flash
Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
  - Latching of Fuses
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
  - Signal Names
- Parallel Programming
- SPI Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
Electrical Characteristics
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- Two-wire Serial Interface Characteristics
- SPI Timing Characteristics
ADC Characteristics – Preliminary Data
ATmega32 Typical Characteristics – Preliminary Data
Register Summary
Instruction Set Summary
Ordering Information
Packaging Information
- 44A
- 40P6
- 44M1
Errata
- ATmega32 Rev. A
Data Sheet Change Log for ATmega32
- Changes from Rev. 2503A-03/02 to Rev. 2503B-10/02
- Changes from Rev. 2503B-10/02 to Rev. 2503C-10/02
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