Rainbow Electronics ATmega32L - Manual (Page 280)

280
ATmega32(L)
2503C–AVR–10/02
Figure 142. Virtual Flash Page Load Register
Virtual Flash Page Read
Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the
number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the
data are automatically transferred from the Flash data page byte by byte. The first 8
cycles are used to transfer the first byte to the internal Shift Register, and the bits that
are shifted out during these 8 cycles should be ignored. Following this initialization, data
are shifted out starting with the LSB of the first instruction in the page and ending with
the MSB of the last instruction in the page. This provides an efficient way to read one full
Flash page to verify programming.
Figure 143. Virtual Flash Page Read Register
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
Machine
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
Machine