Rainbow Electronics DS12887 - Manual (Page 6)

DS12887
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RESET is low should exceed 200ms to ensure that the internal timer that controls the DS12887 on power-
up has timed out. When RESET is low and V
CC
is above 4.25V, the following occurs:
A) Periodic Interrupt Enable (PEI) bit is cleared to 0.
B) Alarm Interrupt Enable (AIE) bit is cleared to 0.
C) Update Ended Interrupt Flag (UF) bit is cleared to 0.
D) Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E) Periodic Interrupt Flag (PF) bit is cleared to 0.
F) The device is not accessible until
RESET is returned high.
G) Alarm Interrupt Flag (AF) bit is cleared to 0.
H) H.
IRQ pin is in the high impedance state.
I) Square-Wave Output Enable ( SQWE ) bit is cleared to 0.
J) Update Ended Interrupt Enable (UIE) is cleared to 0.
In a typical application RESET can be connected to V
CC
. This connection allows the DS12887 to go in
and out of power fail without affecting any of the control registers.
ADDRESS MAP
The address map of the DS12887 is shown in Figure 2. The address map consists of 114 bytes of user
RAM; 10 bytes of RAM that contain the RTC time, calendar, and alarm data; and 4 bytes that are used for
control and status. All 128 bytes can be directly written or read except for the following:
1) Registers C and D are read-only.
2) Bit 7 of Register A is read-only.
3) The high-order bit of the seconds byte is read-only.
The contents of four registers (A, B, C, and D) are described in the Registers section.
Figure 2. ADDRESS MAP