Rainbow Electronics DS12887 - Manual (Page 10)

DS12887
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changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to
read valid time/calendar data to exceed 244
ms.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (Figure 3). Periodic interrupts that
occur at a rate of greater than t
BUC
allow valid time and date information to be reached at each occurrence
of the periodic interrupt. The reads should be complete within one (t
PI/2
+ t
BUC
) to ensure that data is not
read during the update cycle.
Figure 3. UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP