Rainbow Electronics DS12887 User Manual

Page 13

DS12887

13 of 19

REGISTER C

MSB

LSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IRQF

IRQF– The interrupt request flag (IRQF) bit is set to a 1 when one or more of the following are true:

PF = PIE = 1

AF = AIE = 1
UF = UIE = 1

That is, IRQF = PF x PIE + AF x AIE + UF x UIE.

Any time the IRQF bit is a 1, the

IRQ

pin is driven low. All flag bits are cleared after Register C is read

by the program or when the

RESET

pin is low.

PF– The periodic-interrupt flag (PF) is a read-only bit that is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the

IRQ

signal is active and sets the

IRQF bit. The PF bit is cleared by a

RESET

or a software read of Register C.

AF– A 1 in the alarm-interrupt flag (AF) bit indicates that the current time has matched the alarm time. If
the AIE bit is also a 1, the

IRQ

pin goes low and a 1 appears in the IRQF bit. A

RESET

or a read of

UF – The update-ended interrupt flag (UF) bit is set after each update cycle. When the UIE bit is set to 1,
the one in UF causes the IRQF bit to be a 1, which asserts the

IRQ

pin. UF is cleared by reading Register

C or a

RESET

BIT 0, BIT 1, BIT 2, BIT 3 – These are unused bits of the status Register C. These bits always read 0
and cannot be written.

REGISTER D

MSB

LSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

VRT

VRT – The valid RAM and time (VRT) bit is set to the 1 state prior to shipment. This bit is not writable
and should always be a 1 when read. If a 0 is ever present, an exhausted internal lithium energy source is
indicated and both the contents of the RTC data and RAM data are questionable. This bit is unaffected by

RESET

BIT 6, BIT 5, BIT 4, BIT 3, BIT 2, BIT 1, BIT 0– The remaining bits of Register D are not usable.
They cannot be written and, when read, they always read 0.