Rainbow Electronics ATF1504ASL User Manual
Features, Enhanced features

1
Features
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High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
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In-System Programmability (ISP) via JTAG
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Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
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Advanced Power Management Features
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
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Available in Commercial and Industrial Temperature Ranges
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Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
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Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
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JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
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PCI-compliant
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3.3V or 5.0V I/O Pins
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Security Fuse Feature
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
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Output Enable Product Terms
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Transparent – Latch Mode
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Combinatorial Output with Registered Feedback within Any Macrocell
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Three Global Clock Pins
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ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
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Fast Registered Input from Product Term
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Programmable “Pin-keeper” Option
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V
CC
Power-up Reset Option
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Pull-up Option on JTAG Pins TMS and TDI
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Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
High-
performance
Complex
Programmable
Logic Device
ATF1504AS
ATF1504ASL
Rev. 0950N–PLD–07/02
Document Outline
- Features
- Enhanced Features
- Description
- Block Diagram
- Programmable Pin- keeper Option for Inputs and I/Os
- Input Diagram
- Speed/Power Management
- I/O Diagram
- Design Software Support
- Power-up Reset
- Security Fuse Usage
- Programming
- ISP Programming Protection
- DC and AC Operating Conditions
- DC Characteristics
- Pin Capacitance
- AC Characteristics
- Timing Model
- Input Test Waveforms and Measurement Levels
- Output AC Test Loads
- Power-down Mode
- JTAG-BST/ISP Overview
- JTAG Boundary-scan Cell (BSC) Testing
- BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
- BSC Configuration for Macrocell
- PCI Compliance
- PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode
- PCI Voltage-to-current Curves for +5V Signaling in Pull-down Mode
- PCI DC Characteristics
- PCI AC Characteristics
- Using “C” Product for Industrial
- Using “C” Product for Industrial
- Packaging Information